1. Field of the Invention
This invention pertains generally to memory devices for high speed digital computers and the like and, more particularly, to a circuit for the selection and deselection of cells in high-performance integrated circuit memories.
2. Description of Related Art
Semiconductor memory chips such as ECL (emitter coupled logic) bipolar memory chips generally have a relatively large number of memory cells which are organized into an array of bits (columns) and words (rows) in which individual ones of the cells can be addressed for the purpose of writing data thereto and reading data therefrom. A 16K bit random access memory, for example, might have 128 rows and 128 columns of memory cells, with all of the cells in a given row being connected to a single wordline and all of the cells in a given column being connected to a bitline pair.
The cells are connected to the respective lines in parallel, and this results in a relatively large capacitive load which can limit the performance of the memory. A line is generally selected and deselected by applying different voltage levels to it, and the capacitance and the magnitude of the voltage swing limit the speed at which the line can swing between the different voltage levels. This limits the rate at which data can be written and read since one cell must be completely deselected before another cell can be selected in order to have valid data.
In an ECL bipolar memory, the falling transition of the wordline is usually the dominant component of the delay, but the rising transition is also a factor. The faster a wordline is pulled down to its "low" potential (deselected state), the sooner another wordline can be selected and valid data written to or read from it.